Eureka Technology - PCI-X and PCI bus controller resuable IP cores

PCI Bus

Eureka Technology is one of

the first companies to provide

Reusable IP Cores for PCI bus

systems, both 32-bit or 64-bit.

PCI-X Host Bridge

The 64-bit PCI-X host bridge core is optimized to operate in both PCI mode and PCI-X mode. The user interface is a highly efficient and flexible user interface which provides for easy integration with the CPU and other user logic. The core automatically switch between PCI and PCI-X protocol based on the system environment. It supports both PCI version 2.3 and PCI-X version 1.0b.

PCI-X Master/Target

The 64-bit PCI-X master/target core is optimized to operate in both PCI mode and PCI-X mode. The back-end interface is a highly efficient and flexible back-end bus which provides for easy integration with other user logic. The core automatically switch between PCI and PCI-X protocol based on the system environment. It supports both PCI version 2.2 and PCI-X version 1.0.

PCI Master/Target

PCI bus Master/target contains both the functions to initiate PCI bus access as well as to respond to PCI access. The design employs a very user-friendly back-end interface to allow different user logics to communicate with the PCI bus. DMA controller, FIFOs and communication processors can be easily connected to the PCI bus master/target. Target function and configuration registers are included in the design.

64-bit and 32-bit bus sizes are supported
Mini-PCI, Cardbus, Compact PCI and Power Management supports.
Options for asynchronous back-end use interface.

PCI Target

PCI bus target contains functions as a target to all PCI bus accesses. A microprocessor style back-end bus interface allow different user logic to be connected to the target. It sustains zero wait state data transfer indefinitely without the use of any FIFOs. Many different features of the PCI, such as retry, disconnect, and bus abort, are supported.

64-bit and 32-bit bus sizes are supported.
Compact design. Basic design requires less than 3000 gates.
Mini-PCI, Cardbus, Compact PCI and Power Management supports.
Options for asynchronous back-end use interface.

PCI Host Bridge

The PCI host bridge allows different types of host CPUs to access the PCI bus resources and to configure the PCI bus under software control. Many design options are possible on the host bridge.

64-bit and 32-bit bus sizes are supported.
Synchronous or Asynchronous clock between CPU host bus and PCI bus.

AHB to PCI Host Bridge

This controller allows the ARM CPU to initialize and access all PCI devices. It also provides external PCI devices access path to system resources on the AMB AHB bus.

Compliant with PCI spec 2.2.
Upstream and downstream data transfer.
AHB bus and PCI bus runs at different clock domains.
Multiple data buffer to speed up data transfer and prevents deadlock.

PCI-PCI Bridge

The PCI-to-PCI Bridge connects between a primary PCI bus and a secondary PCI bus. Data access is allowed to flow between the two buses in both directions.

PCI-ISA Bridge

The PCI-to-ISA bridge allows PCI masters to access ISA slave devices. It maps a specific address space in the PCI bus to the ISA bus space and convert PCI transactions to ISA transactions.

PCI Arbiter

The PCI bus arbiter arbitrates between multiple bus masters on the PCI bus. Rotating priority, fixed priority and bus parking are implemented. The bus arbiter also supports bus latency time-out and observes bus grant turn-around-time requirements.