PCI Express System Verification
In many complex designs, the verification process is as important as the design process. In developing open systems such PCI Express, the verification process is even more critical because the compatibility requirements. All PCI Express designs such as ASIC, FPGA or adapter boards need to meet the compliance test setup by PCI-SIG, the controlling organization of the PCI Express specification.
In implementing the highly complex PCI Express Specification, Eureka Technology has gone to great lengths to verify and validate the EC310 PCI Express Controller Core. The rigorous validation process for the EC310 consisted of six components:
- Multiple simulation environments, including system level simulation using Bus Functional Models (BFM) and cycle-by-cycle vector based simulation.
- PCI Express Configuration Test suite (PCIE-CV) published by PCI-SIG
- PCI Express Link and Transaction Protocol Test using industrial standard PCI Express Protocol Test Card (PTC) by Agilent Technologies
- Hardware Evaluation and Development Kit, consisting of actual PCI Express boards built with the PCI Express core in silicon, Windows device drivers and application software.
- Interoperability test between Eureka’s PCI Express Controller Core (implemented in silicon) and multiple PCI Express chipsets from various manufacturers
- PCI-SIG Certification
Each step is explained in further detail below:
1. Multiple Simulation Environments
As part of the design process, the EC310 is extensively simulated in two independent environments. The first environment resembles a real life application of the PCI device. The simulation environment consists of
- Bus Functional Models (BFM) of various devices on a PCI Express system,
- BFM of memory models for storing all data transfers,
- Test suites that is capable of generating large amount of data traffic in all directions, and
- Capability to insert error conditions such as bad sequence number, bad CRC or NAK during simulation.
Eureka design the test suite that bus traffic can be generated dynamically on the bus. Many parameters of each bus transaction such as read/write, burst lengths, byte enables, and address can all be generated randomly. This test ensured that packets were can be transmitted and received properly, under various timing conditions, regardless of buffer status, size, type, and transaction order in which each packet arrived.
The second environment is a directed vectors based environment. By utilizing directed vectors, many borderline cases could be tested with precise timing. The vector based simulation environment applies stimulus to the EC310 PCI Express Core every clock cycle and compare its output with the expected vector every clock cycle. The design has to produce the correct vector every clock cycle in order for it to pass the test. Many unusual error conditions easily using this method. For example, vectors can be arranged to have the wrong CRC values, or to force the EC310 core into replay mode. Errors in packet formation, as well as specific order sequences of events are tested as well.
Both the system level test (using BFM) and vector based test can be ran as regression test. Both simulation environment are self-checking. Each automatically flags an error and stop the simulation when error is detected. By using the simulation as regression test, the core can be re-tested easily after any modification or improved is made.
2. PCI Express Configuration Space Test (PCIE-CV)
The EC310 PCI Express IP core is also verified using the PCIe Configuration Space Test suite (PCIE-CV). This test program, developed and provided by the PCI-SIG, performs detailed testing on the configuration registers contained within a PCI Express device. The PCIE-CV is a third party and unbiased test that ensures the EC310 can be properly detected by software, and that it is backwards compatible with standard PCI device.
Using the PCIE-CV is an important transition from software simulation to hardware testing. Before PCIE-CV test can be done, the EC310 PCI Express core has to be implemented in silicon and on a PCI Express adapter board with PHY. All PCI Express electrical requirements must be met. The fact that the EC310 was designed both for ASIC and FPGA implementation and the support of both internal and external PHY simplifies the creation of the PCI Express adapter board.
The test is run on a standard Windows-XP platform, and is hardware independent. The PCIE-CV software installs itself as a PCI driver, and sends commands directly to the EC310 PCI Express device. Utilizing both read and write commands, it can verify 1) that the proper values are advertised by the EC310 device, and 2) that new configurations can be properly programmed. The software tests the configuration topology, register types, standard PCI register space as well as the PCIe extended register space. In addition, the PCI-EV software suite also runs configuration stress tests and link retraining sequences, to ensure proper behavior even when the program is bombarded with hundreds of consecutive requests. The following are the screen shots captured from a PCIE-CV test session.
3. PCI Express Protocol Test Card (PTC)
The PCI Express Protocol Test Card (PTC), an industry standard device developed by Agilent Technology, part number E2969A, plugs in between the device under test and the host system. By locating between the EC310 endpoint device and the host system, the PTC can monitor traffic flow and also inject errors. Simple tests to monitor proper functionality can be run with the PTC in passive mode. More advanced tests have the PTC injecting errors and/or withholding packets from one side.
Once installed in the Windows platform, the PTC is controlled through software, and is specifically designed to test link-layer and transaction-layer behavior. It is capable of generating abnormal conditions that usually won't exist in a properly design PCI Express bus system. It ensures that the EC310 must recover correctly from these conditions and generate the proper error report according to the bus specification. Some of the unique features that the PTC is able to test are:
- Reserved and Undefined Fields in packets.
- This test verified that the EC310 was able to properly ignore reserved fields in various packet types. The EC310 also generates the proper response and error packets when undefined encodings are received.
- LCRC and Sequence number tests.
- These tests verified that the EC310 was able to properly handle incorrect LCRC data and/or sequence numbers. The EC310 automatically detects these sorts of errors and is able to fix and log these problems.
- Timeout tests.
- If the EC310 does not receive a response from the root complex (host system), it automatically retransmits and replays unacknowledged data. If, after multiple tries, a response is still not received, the EC310 will retrain the link in an attempt to re-establish the connection. The PTC simulated these circumstances and verified the proper behavior of the EC310 endpoint controller.
- Duplicate packets.
- The EC310 properly handles receiving duplicate packets by sending an additional acknowledgement packet, but ignoring the duplicate packet otherwise. The PTC simulates this scenario and is able to verify proper behavior.
4. Hardware/Software Evaluation and Development Kit
The hardware validation process was repeated with several adapter boards. This allowed the testing of the core with different PCI Express Physical Layer (PHY) implementations, both for on-chip PHY core and stand-alone PHY chips.
The EC310 PCI Express core supports the standard PIPE interface (Phy Interface for PCI Express) and has proven to support on-chip PHY core such as the Rambus PCI Express PHY cells. It also support other external PHY chips such as the Philips PX1011A and Genesys GL9714 PHY chips. FPGA PHY such as the Xilinx Rocket IO are also supported.
The PCI Express evaluation and demonstration board that Eureka has recently announced consisted of Philips' PX1011A PHY chip, with Eureka's PCI Express Controller Core residing in a Xilinx Spartan 3 device.
In order to demonstrate the functionality of the EC310 PCI Express core in real world applications (other than PCIE-CV and PTC tests), Eureka Technology has created demo program and corresponding device driver, which demonstrates the functionality of the core through a PCI Express capable PC. When plugged into a PCI Express capable PC, the EC310 is quickly identified by the operating system. The ability to see the device in Windows' device manager and install a driver verifies both the proper functionality of the Base Address Registers (BARs) as well as the configuration space.
The installed driver, in conjunction with the demonstration program, allows the user to send read and write commands to the device. The configuration registers can be read, and PIO and DMA accesses can be started. This demonstrates the ability of the EC310 to handle continuous read and write requests in a system. It is also used to demonstrate the ability of the EC310 to take advantage of the available bandwidth. Depending on the host system as well as the configuration of the core, over 90% utilization of the theoretical maximum bandwidth can be achieved.
The following screen shots shows the detection of the evaluation board and the results of the demonstration program.
The evaluation board, device driver, application program and the evaluation license of the EC310 PCI Express core is now available to all Eureka Technology customers. This board is designed to be used as an evaluation board as well as a PCI Express development board. All major function of the development board are implemented in a Spartan3 FPGA. User of the development board can (with proper license) implement his/her specific application logic along with the PCI Express IP core to start product development. Device driver and the application program are provided as source code to customers to speed up software and hardware co-development.
Link to development board
5. Interoperability Testing
To ensure compatibility with various chipsets and BIOS, the EC310 core, along with the development board, was rigorously tested and verified with a wide variety of chipsets/BIOS/system combinations. The chipsets and devices that the EC310 has been tested includes Intel's desktop family such as 915, 925, Intel's server family such as E7525, chipsets from other companies such as nVidia nForce 4, Via Techology and chipsets from other vendors that are currently under NDA. Each of these systems had varying BIOS from leading providers.
In order to stress test the PCI Express core in as many system as possible, Eureka sets up its own test environment with commercially available systems and motherboards, partner with PCI Express developers, and participated in PCI Express plugfest organized by PCI-SIG. Since the core has been extensively tested, user of the PCI Express core are ensured of the core's compatibility with the published standard.
Throughout our extensive test, it is discovered (not unexpectedly) that not all PCI Express systems are created equal. Some PCI Express systems differs from the published standard and he BIOS has a strong influence on the compatibility of a PCI Express system. Interoperability testing across multiple platform is very important to ensure that a new design is compatible not just to a few systems but conformed to the bus standard.
6. PCI-SIG Certification
The final step in the PCI Express core's verification process was attending the PCI-SIG compliance workshop. The week long workshop was a key step in obtaining a place in the PCI-SIG integrators list. This is the only third party PCI Express compliance test available and products must passed the strict compliance testing before it can be certified. It is important to note that the PCI-SIG compliance workshop tests only three classes of products: motherboard, switch and adapter card. Component can be tested only as part of any of the above 3 product classes. For example, a PHY chip vendor cannot bring a PHY chip for PCI-SIG compliance test. There is no capability to test a stand-alone PHY chip. The PHY chip must be tested as part of a PCI Express adapter card. Only when the adapter card passes the test will the PHY be listed as a compliant component.
There were 4 major steps at the compliance workshop:
- The device had to demonstrate the ability to pass the PCIE-CV test on a PCI-SIG system.
- The device had to pass a suite of test programs that were ran with the Protocol Test Card.
- The device had to pass electrical and mechanical testing.
- Finally, the device had to pass interoperability testing. This was a chance for the device to be tested with various system vendors in the same workshop.
In order to pass the interoperability test, a device has to work with at least 80% of the system vendors in the same workshop. The reason for the 80% passing rate, as opposed to a 100% passing rate, is because interoperability success depends on both the system board vendor and the card vendor having correct design. If 100% passing rate is used, any incompatible system board in the workshop will fail all adapter cards. Similarly, a single incompatible card will fail all system boards in the workshop.
After successfully passing the compliance workshop, a detailed checklist (approximately 80 pages) of the products features is filled out and sent to the PCI-SIG. This checklist served as a final reminder to verify that the product was, in fact, designed according to the official specification.
The EC310 has obtained certification as both a component and as an add-in card.
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