What are the differences between PCI Express and conventional PCI?

Is PCI Express the same thing as PCI-X?

What is the difference between a link and a lane?

What is the PCI Express bus performance?

What is the difference between a x1, x4, x8, and x16 PCI Express device?

What are the 3 layers in PCI Express bus architecture?

What is 8-bit/10-bit encoding?

What is SERDES?

What is a PHY?

What is PIPE?

Where can I get PCI Express design resources?

What kind of test equipment do I need for developing PCI Express systems?

How do I develop software for PCI Express systems?

Where can I get the PCI Express bus specification?

How does one get on the PCI-SIG integrators list?

1.

What are the differences between PCI Express and conventional PCI?

A.

PCI Express is a high-performance bus technology that is designed to follow where conventional PCI leaves off. There are several key features in PCI Express that make it the logical successor to conventional PCI:

• PCI Express is a packet based, serial technology, as opposed to the parallel nature of PCI. This greatly reduces the number of pins required, and simplifies board routing and manufacturing.
• PCI Express is a point-to-point technology whereas conventional PCI is a multi-drop bus. In conventional PCI, the bus bandwidth is shared by all devices; only one master device on the bus can communicate with one target device at any given time. In PCI Express, each device has full duplex communication with its neighbor at the same time, thus greatly increase overall system bandwidth.
• PCI Express is fully scalable. The basic data rate (1 lane) doubles that of the 32-bit/33Mhz PCI bus. However, a 16 lane connection has 32 times the data rate of conventional PCI bus, in each direction.

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2.

Is PCI Express the same thing as PCI-X?

A.

No, PCI-X refers to another bus protocol, more similar to PCI than to PCI Express. The proper way to abbreviate PCI Express is to refer to it as PCIe.

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3.

What is the difference between a link and a lane?

A.

Each point-to-point connection within the bus topology between two devices is referred to as a link. For example, a link can be created between an endpoint device and the root complex. Another example of a link might be between the root complex and the switch.

Each link may consists of 1, 4, 8, or 16 traffic lanes. Each lane consists of one differential pair for transmit and one differential pair for receive. Data bandwidth is full scalable with the number of lanes.

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4.

What is the PCI Express bus performance

A.

The 1st generation PCI Express transmits data serially across each lane at 2.5 Gbs in both directions. Due to the 8b/10b encoding scheme used by PCI Express, in which 8 bits of data (1 byte) is transmitted as an encoded 10 bit symbol, the 2.5 Gbs translates into an effective bandwidth of 250 Mbyte/sec, roughly twice that of conventional PCI bus, in each direction.

A 16-lane connection delivers 4Gbyte/sec in each direction, simultaneously.

Future generations of PCI Express are also expected to increase the data transmission rate per lane.

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5.

What is the difference between a x1, x4, x8, and x16 PCI Express device?

A.

The x1, x4, x8, and x16 refer to the number of lanes on a device. The x1 device has 1 lane, while the x16 has 16 lanes. As previously mentioned, each lane has a bandwidth of 250 Mbyte / sec in each direction. The total bandwidth scales linearly with each additional lane.

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6.

What are the 3 layers in PCI Express bus architecture?

A.

The PCI Express bus architecture consists of 3 layers: The transaction layer, the data link layer, and the physical layer. Each layer is built on top of a lower layer. The reason for this type of architecture was so that changes made to one layer could be transparent to the others. For example, when PCI Express moves from the 1st generation signaling (2.5Gb/s) to a 2nd generation, the only change that will need to be made will be inside the physical layer.

The transaction layer is the uppermost layer, and is responsible for turning requests into PCIe packets, and packets back into requests. The data link layer is the middle layer, and is responsible for error detection and correction. The data link layer also makes sure that the packets get sent across in an orderly, timely fashion. Finally the physical layer is responsible for actually sending and receiving the data across the link. The physical layer interacts with the data link layer, and is also responsible for the I/O buffers, serial/parallel conversions, impedance matching, etc.

Eureka's EC310 PCI Express IP core handles all 3 layers seamlessly, and presents a simple user interface that sits on top of the transaction layer.

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7.

What is 8-bit/10-bit encoding ?

A.

The primary purpose of 8 bit /10 bit encoding is to embed a clock signal into the data stream. This eliminates the need for external clock signals. For high speed serial links, embedding the clock signal becomes a necessity due to the increasing difficulty in matching trace lengths on the boards.

8 bit/10 bit encoding takes 8 data bits, and transforms it into a 10 bit word before sending it across the link. On the receive side of the link, the 10 bit word is decoded back to the original 8 bits. The 8B/10B encoding/decoding scheme is used in a variety of serial technologies other than PCI Express, including Ethernet, Fiber Channel, SATA, and SAS.

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8.

What is SERDES?

A.

SERDES stands for SERializer / DESerializer. It is the job of the SERDES to convert between parallel and serial data. This is needed on the PCI Express link because the data is sent across the link serially at very high speed. However, the upper layers all process the data in a more parallel fashion.

SERDES utilizes analog design techniques to achieve very high speed data rate and the design is technology dependent. The job of designing the SERDES and the digital protocol typically falls into different groups of design engineers.

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9.

What is PHY ?

A.

When used in context with PCI Express, a PHY generally refers to either an on-chip IP core or an off-chip device that handles the low level functions of the physical layer. The PHY can be further divided into the Physical Media Attachment Layer (PMA) and Physical Coding Sublayer (PCS). Together they are responsible for the 8b/10b encoding scheme, elastics buffer and SERDES functions.

Using off-chip PHYs help produce a low cost solution for the digital section of the design. By utilization an off-chip PHY, the remaining PCI Express functions can be implemented in a low cost FPGA or ASIC. In contrast, an on-chip PHY core built into an FPGA or ASIC provide higher level of integration and eliminate the board level routing between the PHY and the digital core. This routing is significant for a multi-lane PCI Express design.

The Eureka EC310 PCI Express core has been demonstrated to work with both on-chip and off-chip PHY in working silicon.

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10.

What is PIPE?

A.

PIPE is the abbreviation for the Phy Interface for PCI Express architecture. It is a specification, published by Intel, that defines communication and responsibility between a PHY and a the pure digital section of a PCI Express device.

Even though it is not part of the PCI Express specification, PIPE interface is very important in accelerating the development PCI Express systems. Since the digital section and the analog section of the PCI Express system is typically designed by different groups of engineer, PIPE interface allows each digital core to work with different PHY core or PHY chips.

The Eureka EC310 PCI Express core also utilizes the PIPE specification, which allows it to function with practically any PHY chip or PHY core. It also supports the PXPIPE employed by the Philips PX1011A PHY chip which reduces the pin count between the digital layers and the PHY chip.

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11.

Where can I get PCI Express design resources?

A.

Eureka Technology provides a variety of design resources, including a development system, detailed information regarding how to pass the PCI-SIG compliance program, as well as this PCI Express FAQ. Additional resources can be found on the PCI-SIG home page, which contains additional information on the specification and compliance program.

PCI Express specification is available only from PCI-SIG to its members. There are also several of PCI Express tutorial books that have been published to assist PCI Express developers.

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12.

What kind of test equipment do I need for developing PCI Express systems?

A.

There are two general types of test equipment that are made for PCI Express systems: Analyzers and Exercisers.

Analyzers usually plug in between two devices. For example, an analyzer that is placed in between a root complex and an add-in card captures the traffic going across the bus, and can display them in a easy to read packet format. Complex triggers can be set up to capture the packets at specific events.

Exercisers behave as either a known endpoint, or a known root complex, and can then be used to simulate certain traffic patterns, allowing a broader range of testing.

There are a large number of analyzer/exerciser test equipment companies, including: Agilent, Catalyst, and LeCroy.

One alternative to the potentially expensive analyzer/exerciser solution would be to employ a logic analyzer. While the logic analyzer is not fast enough at 2.5 Gbs, it is fast enough to monitor the PIPE interface, which run at either 125 Mhz or 250 Mhz. Since the logic analyzer does not capture the 2.5Gbs data stream, it can be used only with known good PHY core or PHY chips.

For testing PHY chips and PHY cores, very high speed oscilloscope is needed to capture the eye-diagram and perform other electrical measurements.

For testing add-in cards compliance, a PCI Express protocol test card (PTC) is needed. For more information on compliance test, please go to the PCI verification web page.

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13.

How do I develop software for PCI Express systems ?

A.

From a software point of view, PCI Express systems appear the same as conventional PCI system. Thus, the software development for a PCI Express system would be the same as for a PCI system. All the skills and software tools used for conventional PCI are directly applicable. Typically, a device driver would needed to communicate with an add in card. An application specific software would then be built on top of the device driver.

As part of Eureka's PCI Express development kit, a sample device driver and application software are provided as examples to the user.

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14.

Where can I get the PCI Express bus specification?

A.

The PCI Express bus specification may be obtained from the PCI-SIG, which publishes the PCIe and other specifications. Their web site is www.pcisig.com.

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15.

How does one get on the PCI-SIG integrators list?

A.

To get on the PCI-SIG integrators list, the device must attend and pass a PCI-SIG compliance workshop. The testing at the workshop consists of electrical, logical, and configuration tests run by the PCI-SIG group. A device must also demonstrate interoperability with the various other vendors at the workshop. Finally, a lengthy checklist which details the expected behavior of the device must be submitted to PCI-SIG for approval. For more details on the compliance program, please visit the PCI-SIG compliance page.

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