EC314 4-Lane PCI-Express Bus Controller

See EC310 for 1-Lane PCI Express Endpoint Controller

Features

• Compliant to PCI Express Specification 1.1 for 4-lane end point.
• Supports all 3 layers of PCI Express protocol.
• Simple user interface to send and receive requests from the PCI Express Link with address and data bus.
• Automatically generates and decodes all PCI Express packets and header information.
• Handles all PCI Express protocols, ordering rules, flow control, LCRC, error checking, replay, scrambling and lane training.
• Includes all PCI Express configuration and power management registers.
• Lane reversal and polarity inversion are supported by the core.
• Identical user interface as 1-lane IP core ease design migration.
• High performance design delivers close to 100% of the theoretical bandwidth in real applications.
• Multiple posted requests and pending request queues.
• 4-lane design supports up to 10Gbps.
• Optional AHB user interface and DMA transfer.
• Synthesizable RTL code for ASIC and FPGA implementations.
• Standard PIPE interface supports for on-chip PHY cores and external PHY chips.

Diagram

Description

The EC314 PCI Express Bus Controller functions as an interface to the PCI Express transceiver for a PCI Express Endpoint device. This core supports 4-lane PCI Express link.

This core is designed to handle all PCI Express bus protocol. It allows the chip designer to integrate PCI Express connectivity to his design without going through the time consuming learning curve of PCI Express bus architecture. When this core is integrated to a chip design, the PCI Express bus can be accessed by simple read and write accesses from the user logic. Similarly, external accesses comes from the PCI Express bus is translated into simple memory read and write accesses to the user logic. Different kinds of user logic functions such as micro controller, DMA and SDRAM controller can be integrated with the PCI Express core to gain access to the PCI Express bus.

Asynchronous user interface is supported by the core. It allows the user interface to run in a different clock domain from the PCI Express physical interface. The PCI Express core combines high performance and low cost implementation at the same time. It supports multiple posted and pending requests from the user logic and from the PCI Express link for high performance data transfer. Low cost implementation is achieved through the support of on-chip and off-chip PHY devices through industrial standard PIPE interface. The core is fully synthesizable and can be implemented in ASIC and FPGA.

The master user interface of the core allows single or burst, read or write accesses generated by the user logic. The accesses are converted to Transaction Layer Packets (TLPs) following the definition of the PCI Express Transaction Layer Protocol specification. The transmit FIFO internal to the core can store up to 6 TLPs. The transmit FIFO also allows the user interface and the rest of the core to operate at different clock frequencies. TLPs from the transmit FIFO will be transmitted to the transceiver following the PIPE protocol of the transceiver.

The TLPs constructed from the user accesses are automatically applied with a sequence number and Link Cyclical Redundancy Check (LCRC), following the definition of the PCI Express Data Link Layer Protocol specification, before transmitting to the PCI Express Link. They are stored in an internal retry buffer in case re-transmission is needed due to negative acknowledgement. If re-transmission is needed, it is accomplished automatically with no necessity of user attention.

The accesses from the PCI Express Link are received in the form of TLPs. The core interprets the received TLPs, verifies with the formation rules and are stored in the receive FIFO. The receive FIFO internal to the core can store up to 6 TLPs. The received TLPs are then propagated to the user through the target user interface. If the verification succeeds or fails, the core will automatically construct Data Link Layer Packets (DLLPs) containing positive or negative acknowledge following the definition in the PCI Express Data Link Layer Protocol specification to requestor with no necessity of user attention.

The transmission and reception of the TLPs follows the Flow Control rule defined in the PCI Express Transaction Layer Protocol specification to avoid data overflow. The transmission buffer can store multiple TLPs and this allows continuous transmission of TLPs. While one or more TLP(s) could be waiting for positive acknowledgement, one TLP could be in transmission to the PCI Express bus and one TLP could be under construction from the master user interface. The reception buffer can also store multiple TLPs and this allows continuous reception of TLPs. While one TLP is arriving from the PCI Express Link, one TLP could be propagated to the user logic through the target user interface. The exchange of the Flow Control information is done by the transmission and reception of DLLPs, and the core will automatically achieve this with no necessity of user attention.

The EC314 PCI Express bus controller contains all PCI Express configuration and power management registers. Configuration accesses from the PCI Express bus are automatically processed by the core with no necessity of user attention.

The EC314 PCI Express bus controller automatically performs link initialization and training after startup, following the PCI Express Physical Layer Protocol specification. The core also contains the link training and status state machine which indicates different status states of the Link. For example, this state machine will go to the Reset or Recovery state when a non-recoverable error has happened, to reset or start the re-training sequence depending on the system instruction. The core also performs framing to lanes and data scrambling on TLPs and DLLPs before they are transmitted to the Link.

PHY Device Support

Many different kinds of PHY solutions are supported by the EC314 PCI Express bus controller core. The core supports the standard PIPE interface so it is operable with virtually all PHY devices. Different variation of the PIPE interface such as single data rate, double data rate and/or source clocking are supported..