EP505 EC Interface to SDRAM Controller

Features

• Designed with synthesizable HDL for ASIC and PLD synthesis.
• SDRAM controller interface directly with MIPS EC interface and user interface.
• Built-in arbitration between two access ports.
• Second access port allows memory sharing with user logic devices.
• Dual write buffer for simultaneous write posting and SDRAM access.
• Address pipeline and separate read and write data phases are supported.
• Zero wait state burst data transfer on both MIPS EC interface and SDRAM.
• Operates on both discrete SDRAM chips and PC100/133 SDRAM DIMM.
• Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes.
• Pipeline access allows continues data transfer without wasted cycle.
• Fast page access on row address matching.
• Independent row address matching for each of the 4 SDRAM banks.
• Programmable memory size: 4, 8, 16 and 32 bits per SDRAM.
• Programmable SDRAM access timing parameters.
• Automatic refresh generation with programmable refresh intervals.

Diagram