EP155 MIPS EC Interface Bus Slave

Features

• Designed with synthesizable HDL for ASIC and FPGA synthesis.
• Compliant to the EC Interface of the MIPS CPU.
• Supports MIPS64 5K and MIPS32 4K processor core family.
• Supports separate address and data phases on the EC bus interface.
• Dual write buffers to support write posting.
• Up to 3 bus transfers outstanding at various stage of processing.
• Supports address pipeline by EC interface.
• Out of order access completion and separate read and write data phase.
• Supports both single and burst transfer.
• Sequential ordering burst address sequence.
• Supports any number of wait states in address and data phases.
• Multiple user logics such as the SDRAM controller, PCI host bridge and system control registers can be access through the bus slave.
• Supports parallel write to two different agents at the backend to improve the system performance.
• Address translation between the EC bus address space and the PCI address space.

Diagram