EP150 MIPS SysAD Bus Slave

Features

• Supports 64-bit MIPs CPU bus through the SysAD bus interface.
• Supports single and burst access from CPU.
• Dispatches CPU request to SDRAM controller, FLASH controller, PCI, user interface, and system control registers.
• Supports two outstanding read operation to two groups of data sources.
• Supports out-of-order data return.
• Two write buffers to maximize data bandwidth.
• Centralized control of all access to system control registers by CPU and by user logic.
• Provide access path from CPU to external user logic.
• All input signals from CPU are sampled by flip-flops before propagate to other logic in order to minimized input setup time.
• Address translation between the SysAD bus address space and the PCI address space.
• Boot-mode initialization serial bit stream and CPU reset generation.

Diagram