EP501 NAND Flash Controller

Frequently Asked Questions about NAND Flash

Features

• Supports up to 32 Gbytes of NAND Flash devices with 8 banks.
• Each bank contains up to 5 NAND Flash connected in parallel for 32-bit data and 8-bit ECC.
• Simple user interface designed for easy on-chip integration.
• Programmable support for large block and small block NAND Flash devices.
• Large Flash memory space can be accessed using data and index register method.
• Programmable access timing.
• User has full access to spare data in NAND Flash device.
• No wait state on reading new page by using write-triggered read.
• Support Boot ROM application by automatic page open upon reset.
• Supports two-plane page program and erase for doubling system bandwidth.
• Word-wise ECC adds 8 bits of ECC to each 32-bit word data for single-bit error correction and double bit error detection.
• Page-wise ECC provides single-bit error correction and double bit error detection for each page of data.
• Error logging with ECC correction and detection.
• Interrupt generation based on ECC error.
• Designed for ASIC and FPGA implementations.

Differentiating Features

• CPU bus interface selection
• ECC for word or page length.

Diagram