NAND Flash Controller
Frequently Asked Questions about NAND Flash
- Supports single-level and multi-level cells (SLC and MLC) NAND Flash devices.
- ECC correction with BCH code for up to 60-bit ECC error per 512 or 1k byte data blocks.
- Programmable support for different page and spare column sizess.
- Simple user interface designed for easy on-chip integration.
- Choices of AHB, AXI, Wishbone and Avalon user interface.
- Large Flash memory space can be accessed using data and index register method.
- Programmable access timing.
- Configurable number of banks and devices per bank.
- Supports ONFI standard command interface.
- User has full access to spare data in NAND Flash device.
- Built-in DMA engine for autonomous data transfer.
- Supports boot-from-NAND Flash with and without DMA.
- Write-triggered read operation eliminate long wait state when open new page for read.
- Supports two-plane page program and erase for doubling system bandwidth.
- Compatible with standard FTL and Linux JFFS2 for wear leveling and bad block management. Low level drivers available.
- Option to transfer data with NAND Flash through DMA.
- Designed for ASIC and FPGA implementations.
- Choices of AHB, AXI, PLB, Wishbone and Avalon user interface.
- Different levels of ECC support.
- Built in DMA Controller for boot code and data transfer.