EP500 Flash/ROM/SRAM Controller

Features

• Supports industry standard Asynchronous SRAM, NOR Flash, ROM and similar memory devices.
• Two request ports to allow two requesters to share access to the FLASH/ROM/SRAM devices.
• 8 Chip select signals to access up to 8 memory banks.
• Independent programmable timing parameters for each chip select.
• Independent address mapping for each chip select.
• Independent programmable data width of 8, 16 and 32 bits for each chip select.
• Supports 32-bit and 64-bit user interface bus width.
• Supports burst access from the request ports.
• Automatic issues multiple access to memory device (byte collection) to match data word size of memory device with user interface data width.
• Optional AHB user interface.
• Optional ECC protection.
• Optimzed for logic synthesis for ASIC and FPGA implementations.
• Fully static design with edge triggered flip-flops.

Diagram